View MP8757_9040511.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MP8757 high efficiency, 7a, 18v synchronous , step - down converter MP8757 rev. 1.0 www.monolithicpower.com 1 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. description the MP8757 is a fully - integrated, high frequency, synchronous, rectified, step - down converter. it offers a very compact solution to achieve a 7a output current over a wide input - supply range with excellent load and line regulation. MP8757 empl oys the constant - on - time (cot) control scheme, which provides fast transient response , eases loop stabilization . the cot control scheme provides seamless transition to pfm mode at light load operation which boo s ts the light load efficiency. under voltage lockout is internally set as 4 .5 v . an open drain power good signal indicates output voltage is within its nominal voltage range. full p rotection features include ocp , ovp, and th ermal shut down. MP8757 require s minimum number of external components and a re available in qfn 21 (3mmx4mm) package . features ? wide 5 v to 18 v operating input range ? 7 a continuous output current ? lo w r ds (on) intern al power mosfet s ? proprietary switching loss reduction technique ? internal soft start ? output discharge ? 500khz switching fr equency ? ocp , ovp , uvp protection and t hermal shutdown ? latch off reset via en or power cycle ? output adjustable from 0. 6 04 v to 5.5 v applications ? laptop computer ? tablet pc ? networking systems ? server ? personal video recorders ? flat panel television and monitors ? d istributed power systems all mps parts are lead - free and adhere to the rohs directive. for mps green status, please visit mps website under products, quality assurance page. mps and the future of analog ic technology are r egistered t rademarks of monol ithic power systems, inc. typical application * input voltage range covers down to 5v for lower output voltage applications.
MP8757 C 18 v, high current sync hronous buck convert er MP8757 rev. 1.0 www.monolithicpower.com 2 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. ordering information part number package top marking MP8757gl qfn - 21 (3mmx4mm) see below * for tape & reel, add suffi x C z (e.g. MP8757gl - z) top marking mp: mps prefix; y: year code; w: week code: 8757 : first four digits of the part number; lll: lot number; package reference
MP8757 C 18 v, high current sync hronous buck convert er MP8757 rev. 1.0 www.monolithicpower.com 3 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. absolute maximum rat ings (1) supply voltage v in ................................ ....... 2 4 v v s w ................................ ............... - 0.3v to 24.3 v v sw (30ns) ................................ .......... - 3v to 28 v v sw (5ns) ................................ ............ - 6 v to 28 v v bs t ................................ ................... v sw + 5.5 v v en ................................ ............................... 12 v enable current i en (2) ......... . ...................... 2.5ma all other pins .............................. C 0.3v to + 5 .5 v continuous power dissipation (t a = +25 ? c ) ( 3 ) qfn 21 ................................ ..................... 2 .5 w junction temperature ............................... 150 ? c lead temperature ................................ .... 260 ? c storage temperature ............... - 65 ? c to +150 ? c recommended operating conditions ( 4 ) supply voltage v in .............................. 5 v to 18 v output voltage v out .................... 0. 6 04 v to 5.5 v enable current i en ................................ ....... 1ma operating junction temp . (t j ). - 40 c to +125 c thermal resistance ( 5 ) ja jc qfn - 21 (3 mm x 4 mm) .............. 50 ...... 12 ... ? c/w notes: 1) exceeding these ratings may damage the device. 2) refer to page 1 3 of configuring the en control. 3) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction - to - a mbient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max) - t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 4) the device is not guaranteed to function outside of its operating conditions. 5) measured on jesd51 - 7, 4 - layer pcb .
MP8757 C 18 v, high current sync hronous buck convert er MP8757 rev. 1.0 www.monolithicpower.com 4 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. electrical character istics v in = 12v, t j = 25 ? c, unless otherwise noted. parameters symbol condition min typ max units supply current supply current (shutdown) i sd v en = 0v 0 1 a supply current ( quiescent ) i q v en = 2 v , v fb = 0 .65 v 160 1 90 220 a mosfet h igh - side switch on resistance hs rds - on t j = 25 ? c 25 m l ow - side switch on resistance ls rds - on t j = 25 ? c 12 m switch leakage sw lkg v en = 0v, v sw = 0v 0 1 a current limit low - side valley current limit i limit 9 .5 a switching frequency and minimum off time switching frequency f s w 400 500 600 khz minimum off time ( 6 ) t off 250 300 350 ns over - voltage and under - voltage protection ovp threshold v ovp 125 130 135 %v ref ovp delay t ovp del 2.5 s uvp threshold v u vp 55 60 65 %v ref uvp delay t u vp del 12 s reference and soft start reference voltage v ref 598 604 610 mv feedback current i fb v fb = 0.604 v 10 50 na soft start time t ss 1.6 1.95 ms enable and uvlo e nable input low voltage vil en 1.15 1. 2 5 1.35 v e nable hysteresis v en - hys 1 00 mv e nable input current i en v en = 2v 3 a v en = 0v 0 v cc under voltage lockout threshold rising v cc vth 4.5 4.85 v v cc under voltage lockout threshold hysteresis v cc hys 5 00 mv
MP8757 C 18 v, high current sync hronous buck convert er MP8757 rev. 1.0 www.monolithicpower.com 5 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. elec trical characteristi cs (continued) v in = 12v, t j = 25 ? c , unless otherwise noted. parameters symbol condition min typ max units vcc regulator vcc regulator v cc 4.8 5 .1 5. 3 v vcc load regulation icc= 8 ma 5 % power good fb rising (good) pg vth - hi 95 % v ref fb fall ing (fault) pg vth - lo 85 fb rising (fault) pg vth - hi 115 fb fall ing (good) pg vth - lo 105 power good l ow to high delay pg td 450 s power good sink current capability v pg sink 4ma 0.4 v power good leakage current i pg_leak v pg = 3.3v 1 a thermal protection thermal shutdown ( 6 ) t sd 150 c thermal shutdown hysteresis 25 c note: 6) guaranteed by design.
MP8757 C 18 v, high current sync hronous buck convert er MP8757 rev. 1.0 www.monolithicpower.com 6 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. p in functions pin # name description 1 bst bootstrap. a capacitor connected between sw and bs t pins is required to form a floating supply across the high - side switch driver. 2, 3 sw switch output. connect this pin to the inductor and bootstrap capacitor. this pin is driv en up to the vin voltage by the high - side switch during the on - time of the pwm duty cycle. the inductor current drives the sw pin negative during the off - time. the on - resistance of the low - side switch and the internal diode fixes the negative voltage. use wide and short pcb traces to make the connection. try to minimize the area of the sw pattern. 4 nc not connected. 5 , 6 vout buck regulator output voltage sense. connect this pin to the output capacitor of the regulator directly 7 nc not connected. 8 agnd analog g round. the internal reference is referred to agnd. connect the gnd of the fb divider resistor to agnd for better load regulation. 9 nc not connected. 10,11 exposed pad 20,21 p gnd power ground. use wide pcb traces and multiple vias to make t he connection . 12 exposed pad 19 v in supply voltage. the v in pin supplies power for internal mosfet and regulator. the MP8757 operate s from a + 5 v to + 18 v input rail. an input capacitor is needed to decouple the input rail. use wide pcb traces and multiple vias to make the connection. 13 pg power good output, t he output of this pin is an open drain signal and is high if the output voltage is higher than 9 5 % of the nominal volta ge. there is a delay from fb 9 5 % to pg goes high. 14 fb feedback. an external resistor divider from the output to gnd, tapped to the fb pin, sets the output voltage. place the resistor divider as close to fb pin as possible. avoid vias on the fb traces . 15 g nd ground pin. this pin needs to be connected to either pgnd or agnd for normal operation. 16 vcc internal 5v ldo output. the driver and control circuits are powered from this voltage. decouple with a minimum 1 f ceramic capacitor as close to the p in as possible . x7r or x5r grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. 17 en enable. en is a digital input , which are used to enable or disable the regulators. once en = 1, the regulator output will be turned on; when en=0 , the regulator will be turned off. 18 nc not connected.
MP8757 C 18 v, high current sync hronous buck convert er MP8757 rev. 1.0 www.monolithicpower.com 7 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. typical performance characteristics v in = 12 v, v out = 5 v, l= 2h , t j =+25c, unless otherwise noted.
MP8757 C 18 v, high current sync hronous buck convert er MP8757 rev. 1.0 www.monolithicpower.com 8 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. typical performance characteristics (continued) v in = 12 v, v out = 5 v, l= 2h , t j =+25c, unless otherwise noted.
MP8757 C 18 v, high current sync hronous buck convert er MP8757 rev. 1.0 www.monolithicpower.com 9 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. typical performance characteristics (continued) v in = 12 v, v out = 5 v, l= 2h , t j =+25c, unless otherwise noted.
MP8757 C 18 v, high current sync hronous buck convert er MP8757 rev. 1.0 www.monolithicpower.com 10 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. block diagram figure 1 function al block diagram
MP8757 C 18 v, high current synchro nous buck converter MP8757 rev. 1.0 www.monolithicpower.com 11 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. operation pwm operation the MP8757 is fully integrat ed synchronous rectified step - down switch mode converter. constant - on - time (cot) control is employed to provide fast transient response and easy loop stabilization. at the beginning of each cycle, the high - side mosfet (hs - fet) is turned on when the feedbac k voltage (v fb ) is below the reference voltage (v ref ), which indicates insufficient output voltage. the on period is determined by both the output voltage and input voltage to make the switching frequency fairy constant over input voltage range. after the on period elapses, the hs - fet is turned off, or becomes off state. it is turned on again when vfb drops below v ref . by repeating operation this way, the converter regulates the output voltage. the integrated low - side mosfet (ls - fet) is turned on when the hs - fet is in its off state to minimize the conduction loss. there will be a dead short between input and gnd if both hs - fet and ls - fet are turned on at the same time. its called shoot - through. in order to avoid shoot - through, a dead - time (dt) is internall y generated between hs - fet off and ls - fet on, or ls - fet off and hs - fet on. an internal compensation is applied for cot control to make a more stable operation even when ceramic capacitors are used as output capacitors, this internal compensation will then improve the jitter performance without affect the line or load regulation. heavy - load operation figure 2 heavy load operation w hen the output current is high and the inductor current is always above zero amps, it is called continuous - conduction - mode ( ccm). the ccm mode operation is shown in f igure 2 shown. when v fb is below v ref , hs - mosfet is turned on for a fixed interval which is determined by one - shot on - timer. the one shot timer is controlled by input and output voltage so that the switching frequ ency could be fairly fixed at 500khz for different input/output conditions. when the hs - mosfet is turned off, the ls - mosfet is turned on until next period. in ccm mode operation, the switching frequency is fairly constant and it is called pwm mode. light - load operation with the load decrease s , the inductor current decrease s too. once the inductor current touch es zero, the operation is transition from continuous - conduction - mode (ccm) to dis continuous - conduction - mode (dcm). the light load operation is show n in figure 3 . when v fb is below v ref , hs - mosfet is turned on for a fixed interval. when the hs - mosfet is turned off, the ls - mosfet is turned on until the inductor current reaches zero. in dcm operation, t he v fb does not reach v ref when the inductor curren t is approaching zero. the ls - fet driver turns into tri - state (high z) whenever the inductor current reaches zero. a current modulator takes over the control of ls - fet and limits the inductor current to less than - 1ma. hence, the output capacitors discharg e slowly to gnd through ls - fet. as a result, the efficiency at light load condition is greatly improved. at light load condition, the hs - fet is not turned on as frequently as at heavy load condition. this is called skip mode. at light load or no load condi tion, the output drops very slowly and the MP8757 reduce s the switching frequency naturally and then high efficiency is achieved at light load . figure 3 light load operation
MP8757 C 18 v, high current synchro nous buck converter MP8757 rev. 1.0 www.monolithicpower.com 12 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. as the output current increases from the light load condition, the time period within which the current modulator regulates becomes shorter. the hs - fe t is turned on more frequently. hence , the switching frequency increases correspondingly. the output current reaches the critical level when the current modulator time is zero. the cri tical level of the output current is determined as follows: ( 1 ) it turns into pwm mode once the output current exceeds the critical level. after that, the switching frequency stays fairly constant over the output curre nt range. jitter and fb ramp slope jitter occurs in both pwm and skip modes when noise in the v fb ripple propagates a delay to the hs - fet driver, as shown in figures 4 and 5 . jitter can affect system stability, with noise immunity proportional to the stee pness of v fb s downward slope. however, v fb ripple does not directly affect noise immunity. figure 4 jitter in pwm mode figure 5 jitter in s kip mode operating with out external ramp the traditional constant - on - time control scheme is intrinsically unst able if output capacitors esr is not large enough as an effective current - sense resistor. ceramic capacitors usually can not be used as output capacitor. to realize the stability, the esr value should be chosen as follow: (2) t sw is the switching period. the MP8757 has built in internal ramp compensation to make sure the system is stable even without the help of output capacitors esr; and thus the pure ceramic capacitor solution can be applicant. the pure ceramic capacit or solution can significantly reduce the output ripple, total bom cost and the board area . figure 6 shows a typical output circuit in pwm mode without an external ramp circuit. turn to application information section for design steps without external compe nsation. figure 6 simplified circuit in pwm mode without external ramp compensation when using a large - esr capacitor on the output, add a ceramic capacitor with a value of 10uf or less to in parallel to minimize the effect of esl. operating with externa l ramp compensation the MP8757 is usually able to support ceramic output capacitors without external ramp, however, in some of the cases, the internal ramp may not be enough to stabilize the system, and external ramp compensation is needed. skip to applica tion information section for design steps with external ramp compensation . in out out out s in (v v ) v i 2 l f v ?? ? ? ? ? sw on esr out tt 0.7 2 r c ? ?? ? r 1 r 2 cap sw fb vo l c 4
MP8757 C 18 v, high current synchro nous buck converter MP8757 rev. 1.0 www.monolithicpower.com 13 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. figure 7 simplified circuit in pwm mode with external ramp compensation figure 7 shows a simplified external ramp compensation (r4 and c4) for pwm mode . chose r1, r2, r9 and c4 o f the external ramp to meet the following condition: (3) w here: (4) and the vramp on the v fb can then be estimated as: (5) the downward slope of the v fb ripple then follows (6) as can be seen from equation 6, if there is instability in pwm mode, we can reduce either r4 or c4. if c4 can not be reduced further due to limitation from equation 3, then we c an only reduce r4. for a stable pwm operation, the v slope1 should be design follow equation 7. (7) io is the load current. in skip mode, the downward slope of the v fb ripple is the same whether the external ramp is used or not. fig ure 8 shows the simplified circuit of the skip mode when both the hs - fet and ls - fet are off. figure 8 simplified circuit in skip mode the downward slope of the v fb ripple in skip mode can be determined as follow: ( 8) w here ro is the equivalent load resistor. as described in figure 5, v slope2 in the skip mode is lower than that is in the pwm mode, so it is reasonable that the jitter in the skip mode is larger. if one wants a system with less jitter during light loa d condition, the values of the v fb resistors should not be too big, however, that will decrease the light load efficiency. en control the regulator turns on when en goes high. conversely it turns off when en goes low. for automatic start - up the en pin can be pulled up to input voltage through a resistive voltage divider. choose the values of the pull - up resistor ( r up from vin pin to en pin) and the pull - down resistor (r down from en pin to gnd) to determine the automatic start - up voltage: (9) for example, for r up =150k and r down =51k, the is set at 4.93 v. to avoid noise, a 10nf ceramic capacitor from en to gnd is recommended. there is an internal zener diode on the en pin, which clamps the en pin vol tage to prevent it from running away. the maximum pull up current assuming a worst case 12v internal zener clamp should be less than 1ma. r 1 r 2 ceramic sw fb vo l r 4 c 4 i r 4 i c 4 i fb r 9 12 9 sw 4 1 2 rr 11 r 2 f c 5 r r ?? ? ? ? ? ?? ? ? ? ? ?? r4 c4 fb c4 i i i i ? ? ? in out 12 ramp on 4 4 1 2 9 vv r // r vt r c r // r r ? ? ? ? ?? ? ? ?? ? out ramp slope1 off 4 4 v v v t r c sw on -3 esr out slope1 out out sw on tt + -r c io 10 0.7 2 -v v + 2 l c t -t ? ? ? ?? r 1 r 2 esr cout fb vo r o ? ? ref slope2 1 2 out v v ( r r // ro) c ? ? ?? up down in start down rr v 1.25 (v) r ? ? ?? ? in start v
MP8757 C 18 v, high current synchro nous buck converter MP8757 rev. 1.0 www.monolithicpower.com 14 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. therefore, when en is driven by an external logic signal, the en voltage should be lower than 12 v . when en is connecte d with vin through a pull - up resistor or a resistive voltage divider, the resistance selection should ensure the maximum pull up current less than 1ma. if using a resistive voltage divider and vin higher than 12 v, the allowed minimum pull - up resistor r up s hould meet the following equation: (10) especially, just using the pull - up resistor r up (the pull - down resistor is not connected), the is determined by input uvlo, and the minimum resistor valu e is: (11) a typical pull - up resistor is 499 k? . soft start the MP8757 employ s soft start (ss) mechanism to ensure smooth output during power - up. when the en pin becomes high, the internal reference voltage ramps up gradually; hence, the output voltage ramps up smoothly, as well. once the reference v oltage reaches the target value, the soft start finishes and it enters into steady state operation. if the output is pre - biased to a certain voltage during startup, the ic will disable the switching of both high - side and low - side switches until the voltag e on the internal reference exceeds the sensed output voltage at the fb no de. power good (pg) the MP8757 ha s power - good (pgood) output used to indicate whether the output voltage of the regulator is ready or not . the pgood pin is the open drain of a mosfet . it should be connected to v cc or other voltage source through a resistor (e.g. 100 k , ). after the input voltage is applied, the mosfet is turned on so that the pgood pin is pulled to gnd before ss is ready. after fb voltage reaches 9 5 % of ref voltage, the pgood pin is pulled high after a delay. the pgood delay time is 1 ms . when the fb voltage drops to 85% of ref voltage, the pgood pin will be pulled low. over current protection MP8757 ha s cycle - by - cycle over current limiting control. the current - limit cir cuit employs a "valley" current - sensing algorithm. the part use the rds(on) of the low side mosfet as a current - sensing element. if the magnitude of the current - sense signal is above the current - limit threshold, the pwm is not allowed to initiate a new cyc le. the trip level is fixed internally . the inductor current is monitored by the voltage between gnd pin and sw pin. gnd is used as the positive current sensing node so that gnd should be connected to the source terminal of the bottom mosfet. since the co mparison is done during the high side mosfet off and low side mosfet on state, the oc trip level sets the valley level of the inductor current. thus, the load current at over - current threshold, ioc, can be calculated as follows: ( 1 2 ) in an over - current condition, the current to the load exceeds the current to the output capacitor; thus the output voltage tends to fall off. eventually, it will end up with crossing the under voltage protection threshold and shutdown. and f ault latching can be reset by en going low or power - cycling of vin. over/ under - voltage protection ( ovp/ uv p) MP8757 monitor s a resistor divided feedback voltage to detect over and under voltage. when the feedback voltage becomes higher than 1 15 % of the tar get voltage, the controller will enter dynamic regulation p eriod. during this period, the ls will off when the ls current goes to - 1a, this will then discharge the output and try to keep it within the normal range . if the dynamic regulation can not limit t he increasing of the vo, once the feedback voltage becomes higher than 130% of the feedback voltage, the ovp comparator output goes high and the circuit latches as the high - side mosfet driver off in up down v (v) 12 12 1(ma) r (k ) r (k ) ? ?? ?? in-start v in up v (v) 12 r (k ) 1(ma) ? ?? ? ?? inductor oc i i i _ limit 2
MP8757 C 18 v, high current synchro nous buck converter MP8757 rev. 1.0 www.monolithicpower.com 15 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. and the low - side mosfet turn on acting as an - 1a current so urce . when the feedback voltage becomes lower than 6 0 % of the target voltage, the uvp comparator output goes high if the uv still occurs after 26us delay ; then the fault latch will be triggered --- latches hs off and ls on; the ls fet keeps on until the indu ctor current goes zero . also fault latching can be reset by en going low or power - cycling of vin. uvlo protection the MP8757 has under - voltage lock - out protection (uvlo). when the v cc voltage is higher than the uvlo rising threshold voltage, the part wil l be power ed up. it shuts off when the v cc voltage is lower than the uvlo falling threshold voltage. this is non - latch protection. if an application requires a higher under - voltage lockout (uvlo), use the en pin as shown in figure 9 to adjust the input vol tage uvlo by using two external resistors. it is recommended to use the enable resistors to set the uvlo falling threshold (vstop) above 4 . 5 v. the rising threshold (vstart) should be set to provide enough hysteresis to allow for any input supply variations . figure 9 adjustable uvlo thermal shutdown thermal shutdown is employed in the MP8757 . the junction temperature of the ic is internal ly monitored. if the junction temperature exceeds the threshold value ( typical 150oc), the co nverter shuts off. this is a non - latch protection. there is about 25oc hysteresis. once the junction temperature drops to about 125oc, it initiates a ss. output discharge MP8757 discharge s the output when en=low , or the controller is turned off by the prot ection functions (uvp & ocp, ocp, ovp, uvlo, and thermal shutdown). the part discharge s the output using an internal 6 mosfet. en comparator r up r down en mp 8757 in
MP8757 C 18 v, high current synchro nous buck converter MP8757 rev. 1.0 www.monolithicpower.com 16 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. application informat ion setting the output voltage --- without external compensation the MP8757 can usually support different type of output capacitors , including poscap , electrolytic capacitor and also ceramic capacitors without external ramp c ompensation . the output voltage is then set by feedback resistors r1 and r2. as figure 1 0 shows. figure1 0 simplified circuit of pos capacitor first, choose a value for r2. r2 should be chosen reasonably, a small r2 will lead to considerable quiescent c urrent loss while too large r2 makes the fb noise sensitive. typically, set the current through r2 at around 5 - 10ua will make a good balance between system stability and also the no load loss. then r1 is determined as follow with the output ripple consider ed: (13) is the output ripple , refer to equation (23) . other than feedback resistors, a feed forward cap c4 is usually applied for a better transient performance, especially when ceramic cap s are applied for their small capacitance, a cap value around 100pf - 1nf is suggested for a better transient while also keep the system stable with enough noise immunity. in case the system is noise sensitive because of th e zero induced by this cap , add a r esistor - usually named as r9 between this cap and fb to form a pole, this resistor c an be s et according to equation (16) as in the following section . setting the output voltage D with external compensation figure1 1 simplified circuit of ceramic capacito r if the system is not stable enough w hen low esr ceramic capacitor is used in the output, an external voltage ramp should be added to fb through resistor r4 and capacitor c4. the output voltage is influenced by ramp voltage v ramp besides r divider as sho wn in figure 11. the v ramp can be calculated as shown in equation 5 . r2 should be chosen reasonably, a small r2 will lead to considerable quiescent current loss while too large r2 makes the fb noise sensitive. it is recommended to choose a value within 5k? - 50k? for r2, using a comparatively larger r2 when vo is low, etc., 1.05v, and a smaller r2 when vo is high. and the value of r1 then is determined as follow: (14) the v fb(avg) is the average value on the fb, v fb( avg) varies with the vin, vo, and load condition, etc., its value on the skip mode would be lower than that of the pwm mode, which means the load regulation is strictly related to the v fb(avg) . also the line regulation is related to the v fb(avg) . if one wa nts to gets a better load or line regulation, a lower vramp is suggested, as long as the criterion shown in equation 7 can be met. for pwm operation, v fb(avg) value can be deduced from the equation below. (15) r 1 r 2 cap sw fb vo l c 4 out out ref 12 ref 1 v v v 2 rr v ? ? ? ?? out v ? r 1 r 2 ceramic sw fb vo l r 9 r 4 c 4 2 1 fb(avg) 2 out fb(avg) 4 9 r r= v r - (v -v ) r +r 12 fb( avg) ref ramp 1 2 9 r // r 1 v v v 2 r // r r ? ? ? ?
MP8757 C 18 v, high current synchro nous buck converter MP8757 rev. 1.0 www.monolithicpower.com 17 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. usually, r9 is se t to 0, and it can also be set following equation 16 for a better noise immunity. it should also set to be 5 times smaller than r1//r2 to minimize its influence on vramp. (16) using equation 14 to calculate the r1 ca n be complicated. to simplify the calculation, a dc - blocking capacitor cdc can be added to filter the dc influence from r4 and r9. figure 1 2 shows a simplified circuit with external ramp compensation and a dc - blocking capacitor. with this capacitor, r1 ca n easily be obtained by using the simplified equation for pwm mode operation: (17) cdc is suggested to be at least 10 times larger than c4 for better dc blocking performance, and should also not larger than 0.47uf considering start up performance. in case one wants to use larger cdc for a better fb noise immunity, combined with reduced r1 and r2 to limit the cdc in a reasonable value without affecting the system start up. be noted that even when the cdc is applied, the load an d line regulation are still vramp related. figure12 simplified circuit of ceramic capacitor with dc blocking capacitor input capacitor the input current to the step - down converter is discontinuous and therefore requires a capacitor to supply the ac curre nt to the step - down converter while maintaining the dc input voltage. ceramic capacitors are recommended for best performance and should be placed as close to the v in pin as possible. capacitors with x5r and x7r ceramic dielectrics are recommended becaus e they are fairly stable with temperature fluctuations. the capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated as follows: (18) the worst - case condition occurs at v in = 2v out , where: (19) for simplification, choose the input capacitor with an rms current rating greater than half of the maximum load current. the input ca pacitance value determines the input voltage ripple of the converter. if there is an input voltage ripple requirement in the system, choose the input capacitor that meets the specification. the input voltage ripp le can be estimated as follows: (20) under worst - case conditions where v in = 2v out : (21) output capacitor the output capacitor is required to maintain the dc output voltage. ceramic or poscap capacitors are recommended. the output voltag e ripple can be estimated as: (22) in the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated as: 9 4 sw 1 r 2 c 2f ? ? ? ? ?? ? ? out ref ramp 12 ref ramp 1 (v v v ) 2 rr 1 vv 2 r 1 r 2 ceramic sw fb vo l cdc r 4 c 4 out out cin out in in vv i i (1 ) vv ? ? ? ? out cin i i 2 ? out out out in sw in in in i v v v (1 ) f c v v ? ? ? ? ? ? out in sw in i 1 v 4 f c ? ? ? ? out out out esr sw in sw out vv 1 v (1 ) (r ) f l v 8 f c ? ? ? ? ? ? ? ? ?
MP8757 C 18 v, high current synchro nous buck converter MP8757 rev. 1.0 www.monolithicpower.com 18 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. (23) the output voltage ripple caused by esr is very small. therefore, an external ramp is needed to stabilize the system. the external ramp can be generated through resistor r4 and c apacitor c4. in the case of poscap capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr is high enough to stabilize the system. therefore, an external ramp is not needed. a minimum esr value around 12m? is required to ensure stable operation of the converter. for simplification, the output ripple can be approximated as: (24) maximum output capacitor limitation should be also considered in design application. MP8757 has an around 1.6 ms soft - start time period. if the output capacitor value is too high, the output voltage cant reach the design value during the soft - start time, and then it will fail to regulate. the maximum output capacitor value c o_max can be limited appro ximately by: (25) where, i lim_avg is the average start - up current during soft - start period. t ss is the soft - start time. inductor the inductor is necessary to supply constant current to the output load while being driven by the switched input voltage. a larger - value inductor will result in less ripple current that will result in lower output ripple voltage. however, a larger - value inductor will have a larger physical footprint, higher series resistance, and/or lower saturatio n current. a good rule for determining the inductance value is to design the peak - to - peak ripple current in the inductor to be in the range of 30% to 40% of the maximum output current, and that the peak inductor current is below the maximum switch current limit. the inductance value can be calculated by: (26) where i l is the peak - to - peak inductor ripple current. the inductor should not saturate under the maximum inductor peak current, where the peak inductor current ca n be calculated by: (27) pcb layout guide 1. the high current paths ( p gnd, in, and sw) should be placed very close to the device with short, direct and wide traces. 2. put the input capacitors as close to the in and p gnd pins as p ossible. 3. put the decoupling capacitor as close to the vcc and a gnd pins as possible. place the cap close to vcc if the distance is long. and place >3 vias if via is required to reduce the leakage inductance. 4. keep the switching node sw short and away from the feedback network. 5. the external feedback resistors should be placed next to the fb pin. make sure that there is no via on the fb trace. 6. keep the bst voltage path (bst, c3, and sw) as short as possible. 7. keep the i n and p gnd pads connected with large copper and use at least two layers for in and p gnd trace to achieve better thermal performance. also, a dd several vias with 10mil_drill/18mil_copper_width close to the in and p gnd pads to help on thermal dissipation. 8. fo ur - layer layout is strongly recommended to achieve better thermal performance. note : please refer to the pcb layout application note for more details. out out out 2 sw out in vv v (1 ) 8 f l c v ? ? ? ? ? ? ? out out out esr sw in vv v (1 ) r f l v ? ? ? ? ? ? o _ max lim _ avg out ss out c (i i ) t / v ? ? ? out out sw l in vv l (1 ) f i v ? ? ? ?? out out lp out sw in vv i i (1 ) 2f l v ? ? ? ? ?
MP8757 C 18 v, high current synchro nous buck converter MP8757 rev. 1.0 www.monolithicpower.com 19 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. figure 13 recommend layout recommend design example some design example s are provided below when the ceramic capacitors are applied : table 2 design example v out (v) cout (f) l ( h ) r4 ( ? ) c4 (f) r1 (k ? ) r2 (k ? ) 1.05 22 x3 1. 2 ns 220p 59 82 1.2 22 x3 1. 2 ns 220p 100 102 1.35 22 x3 1 .2 ns 220p 100 82 3.3 22ux4 2 1m 220p 88.7 18 5 22ux4 2 1m 220p 150 18 the detailed application schematic is shown in fig ure 14 and figure 15 fo r 1.35v and 5v applications when low esr caps are applied . the typical performance and circuit waveforms have been shown in the typical performance characteristics section. for more possible applications of this device, please refer to related evaluation b oard data sheets. 9 s w 1 7 1 6 1 4 e n p g n d v c c 1 3 p g v i n 1 2 1 5 g n d 1 9 v i n 2 0 p g n d 2 1 p g n d 1 2 3 5 6 7 8 4 t o a g n d 1 1 1 0 v o u t a g n d k e l v i n c o n n e c t t o p g n d a t v c c c a p v i n v o u t v o u t d o n o t c o n n e c t t o p g n d h e r e f b a t l e a s t t w o l a y e r s s h o u l d b e a p p l i e d f o r v i n a n d p g n d a n d p l a c e > 2 0 v i a s c l o s e t o t h e p a r t f o r a b e t t e r t h e r m a l p e r f o r m a n c e 1 8 p g n d a g n d a g n d a g n d - - t o p l a y e r - - v i a - - b o t t o m l a y e r - - i n n e r p g n d l a y e r - - i n n e r l a y e r 2 - - v i a f o r a g n d p g n d b s t n c n c v o u t n c n c
MP8757 C 18 v, high current synchro nous buck converter MP8757 rev. 1.0 www.monolithicpower.com 20 5/1/2018 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. typical application figure 1 4 typical application circuit with low esr ceramic output capacitor v in = 5 - 18 v , v out =1. 35 v f b b s t v i n p g s w e n m p 8 7 5 7 p g n d v o u t v c c g n d 2 2 f v i n 5 - 1 8 v 1 . 3 5 v 4 . 7 2 2 0 n f 4 9 9 k 1 0 0 k 1 f 8 2 k 1 0 0 k 2 2 f x 3 1 . 2 h 2 2 f c e r a m i c c a p n s 2 2 0 p f 4 9 9 v o u t a g n d e n f b b s t v i n p g s w m p 8 7 5 7 p g n d v o u t v c c g n d 2 2 f v i n 7 - 1 8 v 5 v 4 . 7 2 2 0 n f 4 9 9 k 1 0 0 k 1 f 1 8 k 1 5 0 k 2 2 f x 4 2 h 2 2 f c e r a m i c c a p 2 2 0 p f 4 9 9 1 m f i g u r e 1 5 C t y p i c a l a p p l i c a t i o n c i r c u i t w i t h l o w e s r c e r a m i c o u t p u t c a p a c i t o r v i n = 7 - 1 8 v , v o u t = 5 v a g n d v o u t
MP8757 C 18 v, high current sync hronous buck convert er notice: the information in this document is subject to change without notice. please contact mps for current specifications. users should warrant and guarantee that third party i ntellectual p roperty r ights are not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP8757 rev. 1.0 www.monolithicpower.com 21 5/1/2018 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2018 mps . all rights reserved. package information qfn 21 ( 3 mm x 4mm) s i d e v i e w b o t t o m v i e w n o t e : 1 ) a l l d i m e n s i o n s a r e i n m i l l i m e t e r s . 2 ) e x p o s e d p a d d l e s i z e d o e s n o t i n c l u d e m o l d f l a s h . 3 ) l e a d c o p l a n a r i t y s h a l l b e 0 . 1 0 m i l l i m e t e r s m a x . 4 ) j e d e c r e f e r e n c e i s m o - 2 2 0 . 5 ) d r a w i n g i s n o t t o s c a l e . p i n 1 i d m a r k i n g t o p v i e w p i n 1 i d i n d e x a r e a r e c o m m e n d e d l a n d p a t t e r n p i n 1 i d 0 . 1 0 x 4 5 t y p . 0 . 1 0 x 4 5

▲Up To Search▲

Price & Availability of MP8757

	To Download MP8757 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .